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| geometry process details principal device types 2n3439 2n3440 cmpta42 cmpta44 cmpt6517 cxta44 czta42 czta44 mpsa42 mpsa44 gross die per 5 inch wafer 25,214 process cp310 small signal transistor npn - high voltage transistor chip process epitaxial planar die size 26 x 26 mils die thickness 9.0 mils base bonding pad area 6.1 x 4.9 mils emitter bonding pad area 5.2 x 5.2 mils top side metalization al - 30,000? back side metalization au - 18,000? www.centralsemi.com r4 (22-march 2010)
process cp310 typical electrical characteristics www.centralsemi.com r4 (22-march 2010) |
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